/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

/** *****************************************************************************************************
 * \file     Wdg_Ip.c                                                                                   *
 * \brief    AUTOSAR 4.3.1 MCAL can Driver                                                              *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2023/07/25     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/

/********************************************************************************************************
 *                                      Include header files                                            *
 *******************************************************************************************************/
#include "__regs_base.h"
#include "Mcal_Delay.h"
#include "Wdg_Reg.h"
#include "RegHelper.h"
#include "Wdg_Ip.h"
#include "Wdg_Cfg.h"
#include "Compiler.h"
#include "Wdg_Fault.h"
#ifdef __cplusplus
extern "C" {
#endif

/**
 *  \name WDG Driver ID Info
 *  @{
 */
/** \brief SemiDriver Instruments Vendor ID */
#define WDG_IP_C_VENDOR_ID    0x8C
/**
 *  \name WDG Driver Module AUTOSAR Version Info
 *
 *  Defines for WDG Driver AUTOSAR version used for compatibility checks
 *  @{
 */
/** \brief AUTOSAR Major version specification implemented by WDG Driver */
#define WDG_IP_C_AR_RELEASE_MAJOR_VERSION    4
/** \brief AUTOSAR Minor  version specification implemented by WDG Driver */
#define WDG_IP_C_AR_RELEASE_MINOR_VERSION    3
/** \brief AUTOSAR Patch version specification implemented by WDG Driver */
#define WDG_IP_C_AR_RELEASE_REVISION_VERSION 1
/* @} */
/**
 *  \name WDG Driver Module SW Version Info
 *
 *  Defines for WDG Driver version used for compatibility checks
 *  @{
 */
/** \brief Driver Implementation Major Version */
#define WDG_IP_C_SW_MAJOR_VERSION    1
/** \brief Driver Implementation Minor Version */
#define WDG_IP_C_SW_MINOR_VERSION    0
/** \brief Driver Implementation Patch Version */
#define WDG_IP_C_SW_PATCH_VERSION    0
/* @} */
/********************************************************************************************************
 *                                 Global Macro definition                                              *
 *******************************************************************************************************/
/** \brief wdt check register write value correct's times */
#define WDT_IP_WAIT_CHECK_TIMES (10000U)
/** \brief wdt time cnt from 1 start count,so add 1 form parameters */
#define WDT_IP_CNT_COUNT      (0x1U)
/** \brief Driver function enable*/
#define WDG_IP_FUNCTION_ENABLE  (0x1u)
/** \brief Driver function disable*/
#define WDG_IP_FUNCTION_DISABLE  (0x0u)
/** \brief Driver Wdg main clk div number */
#define WDG_IP_CLK_DIV_NUM_SF (23999U)
/** \brief Driver Wdg main clk div number */
#define WDG_IP_CLK_DIV_NUM_LP (31U)
/** \brief Driver Wdg main clk*/
#define WDG_IP_CLK_SRC_MAIN (0U)
/** \brief Driver Wdg global reset control offset*/
#define WDG_IP_GLOBAL_RESET_CONTROL_OFF              (0x204U)
/** \brief Driver Wdg set bit wait time*/
#define WDG_IP_WAIT_TIMEOUT_TIME              (10U)
/** \brief Delay time for waiting for the LP Wdg to be ready. */
#define DELAY_US                                (240ULL)

/** \brief Driver Wdg global reset control offset*/
#define WDG_IP_GLOBAL_RESET_CONTROL_3BIT_VAL          (7UL)
#define WDG_IP_GLOBAL_RESET_CONTROL_2BIT_VAL          (3UL)
#define WDG_IP_GLOBAL_RESET_CONTROL_1BIT_VAL          (1UL)
/** \brief Driver Wdg global reset WDT6 BIT offset*/
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT6_OFF1         (14U)
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT6_OFF2         (6U)
/** \brief Driver Wdg global reset WDT5 BIT offset*/
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT5_OFF1         (13U)
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT5_OFF2         (5U)
/** \brief Driver Wdg global reset WDT4 BIT offset*/
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT4_OFF1         (12U)
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT4_OFF2         (4U)
/** \brief Driver Wdg global reset WDT3 BIT offset*/
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT3_OFF1         (11U)
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT3_OFF2         (3U)
/** \brief Driver Wdg global reset WDT2 BIT offset*/
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT2_OFF2         (15U)
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT2_OFF1         (7U)
/** \brief Driver Wdg global reset WDT1 BIT offset*/
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT1_OFF2         (11U)
#define WDG_IP_GLOBAL_RESET_CONTROL_WDT1_OFF1         (3U)

/** \brief Driver Wdg ctrl soft reset BIT offset*/
#define WDT_CTRL_SOFT_RST_OFF    (0U)
/** \brief Driver Wdg ctrl wdt enable status BIT offset*/
#define WDT_CTRL_WDT_EN_STA_OFF  (10U)
/** \brief Driver Wdg functinal irq enable BIT offset*/
#define WDT_INT_FUNC_EN_OFF      (9U)
/** \brief Drive Wdg irq status BIT offset*/
#define WDT_INT_STA_OFF          (3U)
/** \brief Drive Wdg functinal irq enable BIT mask*/
#define BM_WDT_INT_EN (BM_WDT_INT_OVFLOW_FUNC_INT_EN | BM_WDT_INT_ILL_SEQ_REFR_FUNC_INT_EN | BM_WDT_INT_ILL_WIN_REFR_FUNC_INT_EN)
/** \brief Drive Wdg irq status BIT mask*/
#define BM_WDT_INT_STA (BM_WDT_INT_OVFLOW_INT_STA | BM_WDT_INT_ILL_SEQ_REFR_INT_STA | BM_WDT_INT_ILL_WIN_REFR_INT_STA)
/** \brief Drive Wdg irq status clear BIT mask*/
#define BM_WDT_INT_STA_CLR (BM_WDT_INT_OVFLOW_INT_CLR | BM_WDT_INT_ILL_SEQ_REFR_INT_CLR | BM_WDT_INT_ILL_WIN_REFR_INT_CLR)

/********************************************************************************************************
 *                                  Global Variable Declarations                                        *
 *******************************************************************************************************/
/** \brief  please input Global Variable Declarations information */

#if ((WDG_INSTANCE1_SUPPORT == STD_ON)\
  || (WDG_INSTANCE2_SUPPORT == STD_ON)\
  || (WDG_INSTANCE3_SUPPORT == STD_ON)\
  || (WDG_INSTANCE4_SUPPORT == STD_ON)\
  || (WDG_INSTANCE5_SUPPORT == STD_ON)\
  || (WDG_INSTANCE6_SUPPORT == STD_ON)\
  || (WDG_INSTANCE8_SUPPORT == STD_ON)\
  || (WDG_INSTANCE9_SUPPORT == STD_ON))

#if (WDG_INSTANCE1_SUPPORT == STD_ON)
#define WDG_140_INSTANCE1_WDT_START_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance1_Wdt_MemMap.h"
static uint32 Wdg1_Ip_TimeRatio LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
static uint32 Wdg1_TimeoutCounter LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */
#define WDG_140_INSTANCE1_WDT_STOP_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance1_Wdt_MemMap.h"
#endif /*WDG_INSTANCE1_SUPPORT*/
#if (WDG_INSTANCE2_SUPPORT == STD_ON)
#define WDG_140_INSTANCE2_WDT_START_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance2_Wdt_MemMap.h"
static uint32 Wdg2_Ip_TimeRatio LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
static uint32 Wdg2_TimeoutCounter LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */
#define WDG_140_INSTANCE2_WDT_STOP_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance2_Wdt_MemMap.h"
#endif /*WDG_INSTANCE2_SUPPORT*/
#if (WDG_INSTANCE3_SUPPORT == STD_ON)
#define WDG_140_INSTANCE3_WDT_START_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance3_Wdt_MemMap.h"
static uint32 Wdg3_Ip_TimeRatio LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
static uint32 Wdg3_TimeoutCounter LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */
#define WDG_140_INSTANCE3_WDT_STOP_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance3_Wdt_MemMap.h"
#endif /*WDG_INSTANCE3_SUPPORT*/
#if (WDG_INSTANCE4_SUPPORT == STD_ON)
#define WDG_140_INSTANCE4_WDT_START_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance4_Wdt_MemMap.h"
static uint32 Wdg4_Ip_TimeRatio LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
static uint32 Wdg4_TimeoutCounter LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */
#define WDG_140_INSTANCE4_WDT_STOP_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance4_Wdt_MemMap.h"
#endif /*WDG_INSTANCE4_SUPPORT*/
#if (WDG_INSTANCE5_SUPPORT == STD_ON)
#define WDG_140_INSTANCE5_WDT_START_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance5_Wdt_MemMap.h"
static uint32 Wdg5_Ip_TimeRatio LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
static uint32 Wdg5_TimeoutCounter LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */
#define WDG_140_INSTANCE5_WDT_STOP_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance5_Wdt_MemMap.h"
#endif /*WDG_INSTANCE5_SUPPORT*/
#if (WDG_INSTANCE6_SUPPORT == STD_ON)
#define WDG_140_INSTANCE6_WDT_START_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance6_Wdt_MemMap.h"
static uint32 Wdg6_Ip_TimeRatio LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
static uint32 Wdg6_TimeoutCounter LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */
#define WDG_140_INSTANCE6_WDT_STOP_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance6_Wdt_MemMap.h"
#endif /*WDG_INSTANCE6_SUPPORT*/
#if (WDG_INSTANCE8_SUPPORT == STD_ON)
#define WDG_140_INSTANCE8_WDT_START_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance8_Wdt_MemMap.h"
static uint32 Wdg8_Ip_TimeRatio LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
static uint32 Wdg8_TimeoutCounter LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */
#define WDG_140_INSTANCE8_WDT_STOP_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance8_Wdt_MemMap.h"
#endif /*WDG_INSTANCE8_SUPPORT*/
#if (WDG_INSTANCE9_SUPPORT == STD_ON)
#define WDG_140_INSTANCE9_WDT_START_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance9_Wdt_MemMap.h"
static uint32 Wdg9_Ip_TimeRatio LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
static uint32 Wdg9_TimeoutCounter LOCATE_ALIGNED(WDG_CONFIG_ARCH_CACHE_LINE);
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */
#define WDG_140_INSTANCE9_WDT_STOP_SEC_INTERNAL_VAR_NO_INIT_UNSPECIFIED
#include "Wdg_140_Instance9_Wdt_MemMap.h"
#endif /*WDG_INSTANCE9_SUPPORT*/
/********************************************************************************************************
 *                                  Global Function Declarations                                        *
 *******************************************************************************************************/

/** *****************************************************************************************************
 * \brief  Get the instanceId Watchdog base addr.
 *
 * \verbatim
 * Syntax             : uint32 Wdg_Ip_GetBaseAddr(uint8 instanceId)
 *
 * Service ID[hex]    : none
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : baseAddr
 *
 * Description        : Get the instanceId Watchdog base addr.
 *
 * \endverbatim
 * Traceability       : SWSR_WDG_007
 *******************************************************************************************************/
#define WDG_START_SEC_CODE_FAST
#include "Wdg_MemMap.h"
static uint32 Wdg_Ip_GetBaseAddr(uint8 instanceId)
{
    uint32 baseAddr;
    WdgHookBegin_InvalidInstanceVarInject();
    /*PRQA S 3352 60*/
    switch (instanceId)
    {
        /*#10 judge instanceId whether is WDG_INSTANCE1*/
#if (WDG_INSTANCE1_SUPPORT == STD_ON)

    case WDT1_INDEX:
        baseAddr = APB_WDT1_BASE;
        break;
#endif /*WDG_INSTANCE1_SUPPORT*/
        /*#20 judge instanceId whether is WDG_INSTANCE2*/
#if (WDG_INSTANCE2_SUPPORT == STD_ON)

    case WDT2_INDEX:
        baseAddr = APB_WDT2_BASE;
        break;
#endif /*WDG_INSTANCE2_SUPPORT*/
        /*#30 judge instanceId whether is WDG_INSTANCE3*/
#if (WDG_INSTANCE3_SUPPORT == STD_ON)

    case WDT3_INDEX:
        baseAddr = APB_WDT3_BASE;
        break;
#endif /*WDG_INSTANCE3_SUPPORT*/
        /*#40 judge instanceId whether is WDG_INSTANCE4*/
#if (WDG_INSTANCE4_SUPPORT == STD_ON)

    case WDT4_INDEX:
        baseAddr = APB_WDT4_BASE;
        break;
#endif /*WDG_INSTANCE4_SUPPORT*/
        /*#50 judge instanceId whether is WDG_INSTANCE5*/
#if (WDG_INSTANCE5_SUPPORT == STD_ON)

    case WDT5_INDEX:
        baseAddr = APB_WDT5_BASE;
        break;
#endif /*WDG_INSTANCE5_SUPPORT*/
        /*#60 judge instanceId whether is WDG_INSTANCE6*/
#if (WDG_INSTANCE6_SUPPORT == STD_ON)

    case WDT6_INDEX:

        baseAddr = APB_WDT6_BASE;

        break;
#endif /*WDG_INSTANCE6_SUPPORT*/
        /*#70 judge instanceId whether is WDG_INSTANCE8*/
#if (WDG_INSTANCE8_SUPPORT == STD_ON)

    case WDT8_INDEX:
        baseAddr = APB_WDT8_BASE;
        break;
#endif /*WDG_INSTANCE8_SUPPORT*/
        /*#80 judge instanceId whether is WDG_INSTANCE9*/
#if (WDG_INSTANCE9_SUPPORT == STD_ON)

    case WDT9_INDEX:
        baseAddr = APB_WDT9_BASE;
        break;
#endif /*WDG_INSTANCE9_SUPPORT*/

    default:
        baseAddr = WDT_IP_ZERO;
        break;
    }
    WdgHookEnd_InvalidInstanceVarInject();
    return baseAddr;
}
#define WDG_STOP_SEC_CODE_FAST
#include "Wdg_MemMap.h"

#define WDG_START_SEC_CODE
#include "Wdg_MemMap.h"
/** *****************************************************************************************************
 * \brief Get the time ratio for 24MHZ clk frequence
 *
 * \verbatim
 * Syntax             : uint32 Wdg_Ip_GetTimeRatio(uint8 instanceId)
 *
 * Service ID[hex]    : none
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : timeRatio
 *
 * Description        : Get the time ratio for 24MHZ clk frequence
 *
 * \endverbatim
 * Traceability       : SWSR_WDG_008 SWSR_WDG_021 SWSR_WDG_029 SWSR_WDG_030 SWSR_WDG_031
 *                      SWSR_WDG_032 SWSR_WDG_033 SWSR_WDG_034
 *******************************************************************************************************/
static uint32 Wdg_Ip_GetTimeRatio(uint8 instanceId)
{
    uint32 timeRatio;
    WdgHookBegin_InvalidInstanceRatioInject();
    /*PRQA S 3352 56*/
    switch (instanceId)
    {
        /*#10 judge instanceId whether is WDG_INSTANCE1*/
#if (WDG_INSTANCE1_SUPPORT == STD_ON)

    case WDT1_INDEX:
        timeRatio = Wdg1_Ip_TimeRatio;
        break;
#endif /*WDG_INSTANCE1_SUPPORT*/
        /*#20 judge instanceId whether is WDG_INSTANCE2*/
#if (WDG_INSTANCE2_SUPPORT == STD_ON)

    case WDT2_INDEX:
        timeRatio = Wdg2_Ip_TimeRatio;
        break;
#endif /*WDG_INSTANCE2_SUPPORT*/
        /*#30 judge instanceId whether is WDG_INSTANCE3*/
#if (WDG_INSTANCE3_SUPPORT == STD_ON)

    case WDT3_INDEX:
        timeRatio = Wdg3_Ip_TimeRatio;
        break;
#endif /*WDG_INSTANCE3_SUPPORT*/
        /*#40 judge instanceId whether is WDG_INSTANCE4*/
#if (WDG_INSTANCE4_SUPPORT == STD_ON)

    case WDT4_INDEX:
        timeRatio = Wdg4_Ip_TimeRatio;
        break;
#endif /*WDG_INSTANCE4_SUPPORT*/
        /*#50 judge instanceId whether is WDG_INSTANCE5*/
#if (WDG_INSTANCE5_SUPPORT == STD_ON)

    case WDT5_INDEX:
        timeRatio = Wdg5_Ip_TimeRatio;
        break;
#endif /*WDG_INSTANCE5_SUPPORT*/
        /*#60 judge instanceId whether is WDG_INSTANCE6*/
#if (WDG_INSTANCE6_SUPPORT == STD_ON)

    case WDT6_INDEX:
        timeRatio = Wdg6_Ip_TimeRatio;
        break;
#endif /*WDG_INSTANCE6_SUPPORT*/
        /*#70 judge instanceId whether is WDG_INSTANCE8*/
#if (WDG_INSTANCE8_SUPPORT == STD_ON)

    case WDT8_INDEX:
        timeRatio = Wdg8_Ip_TimeRatio;
        break;
#endif /*WDG_INSTANCE8_SUPPORT*/
        /*#80 judge instanceId whether is WDG_INSTANCE9*/
#if (WDG_INSTANCE9_SUPPORT == STD_ON)

    case WDT9_INDEX:
        timeRatio = Wdg9_Ip_TimeRatio;
        break;
#endif /*WDG_INSTANCE9_SUPPORT*/

    default:
        timeRatio = WDT_IP_ZERO;
        break;
    }
    WdgHookEnd_InvalidInstanceRatioInject();
    return timeRatio;
}

/** *****************************************************************************************************
 * \brief Set the time ratio for 24MHZ clk frequence
 *
 * \verbatim
 * Syntax             : void Wdg_Ip_SetTimeRatio(uint32 timeRatio,uint8 instanceId)
 *
 * Service ID[hex]    : none
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (in)    : timeRatio - 24MHZ clk frequence after div period .
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : Set the time ratio for 24MHZ clk frequence
 *
 * \endverbatim
 * Traceability       : SWSR_WDG_008 SWSR_WDG_021 SWSR_WDG_029 SWSR_WDG_030 SWSR_WDG_031
 *                      SWSR_WDG_032 SWSR_WDG_033 SWSR_WDG_034
 *******************************************************************************************************/
static void Wdg_Ip_SetTimeRatio(uint32 timeRatio, uint8 instanceId)
{
    /*PRQA S 3352 56*/
    switch (instanceId)
    {
        /*#10 judge instanceId whether is WDG_INSTANCE1*/
#if (WDG_INSTANCE1_SUPPORT == STD_ON)

    case WDT1_INDEX:
        Wdg1_Ip_TimeRatio = timeRatio;
        break;
#endif /*WDG_INSTANCE1_SUPPORT*/
        /*#20 judge instanceId whether is WDG_INSTANCE2*/
#if (WDG_INSTANCE2_SUPPORT == STD_ON)

    case WDT2_INDEX:
        Wdg2_Ip_TimeRatio = timeRatio;
        break;
#endif /*WDG_INSTANCE2_SUPPORT*/
        /*#30 judge instanceId whether is WDG_INSTANCE3*/
#if (WDG_INSTANCE3_SUPPORT == STD_ON)

    case WDT3_INDEX:
        Wdg3_Ip_TimeRatio = timeRatio;
        break;
#endif /*WDG_INSTANCE3_SUPPORT*/
        /*#40 judge instanceId whether is WDG_INSTANCE4*/
#if (WDG_INSTANCE4_SUPPORT == STD_ON)

    case WDT4_INDEX:
        Wdg4_Ip_TimeRatio = timeRatio;
        break;
#endif /*WDG_INSTANCE4_SUPPORT*/
        /*#50 judge instanceId whether is WDG_INSTANCE5*/
#if (WDG_INSTANCE5_SUPPORT == STD_ON)

    case WDT5_INDEX:
        Wdg5_Ip_TimeRatio = timeRatio;
        break;
#endif /*WDG_INSTANCE5_SUPPORT*/
        /*#60 judge instanceId whether is WDG_INSTANCE6*/
#if (WDG_INSTANCE6_SUPPORT == STD_ON)

    case WDT6_INDEX:
        Wdg6_Ip_TimeRatio = timeRatio;
        break;
#endif /*WDG_INSTANCE6_SUPPORT*/
        /*#70 judge instanceId whether is WDG_INSTANCE8*/
#if (WDG_INSTANCE8_SUPPORT == STD_ON)

    case WDT8_INDEX:
        Wdg8_Ip_TimeRatio = timeRatio;
        break;
#endif /*WDG_INSTANCE8_SUPPORT*/
        /*#80 judge instanceId whether is WDG_INSTANCE9*/
#if (WDG_INSTANCE9_SUPPORT == STD_ON)

    case WDT9_INDEX:
        Wdg9_Ip_TimeRatio = timeRatio;
        break;
#endif /*WDG_INSTANCE9_SUPPORT*/

    default:
        /*do nothing*/
        break;
    }
}


/** *****************************************************************************************************
 * \brief This service wait ctrl register releatcate register bit clear or set.
 *
 * \verbatim
 * Syntax             : static Std_ReturnType  Wdg_Ip_WaitCtrlBaseState(uint32 base,uint32 offset,boolean val)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base  - Wdg Instance id base Addr
 *
 * Parameters (in)    : offset  - ctrl register offset bit
 *
 * Parameters (in)    : val - wait expect val
 *
 * Parameters (out)   : None
 *
 * Return value       : E_OK\E_NOT_OK
 *
 * Description        : This service wait ctrl register releatcate register bit clear or set.
 * \endverbatim
 * Traceability       : SWSR_WDG_007 SWSR_WDG_011 SWSR_WDG_012 SWSR_WDG_013
 *                      SWSR_WDG_014 SW_SM005
 *******************************************************************************************************/
static Std_ReturnType  Wdg_Ip_WaitCtrlBaseState(uint32 base, uint32 offset, boolean val)
{
    uint32 tms = WDT_IP_ZERO;
    Std_ReturnType ret = E_NOT_OK;
    uint32 wdtSta;
    uint32 count = ((WDT_IP_WAIT_CHECK_TIMES / WDT_IP_WAIT_CHECK_TIMES) * 750UL);

    /*#10 null point check*/
    wdtSta = ((REG_READ32(base + WDT_CTRL_OFF) >> offset) & WDG_IP_FUNCTION_ENABLE);

    WdgHookBegin_Wdg_Ip_TimeoutCheck();
    /*#20 wait base state clear or set*/
    while ((tms < count) && (wdtSta != val))
    {
        WdgHookBegin_TimeoutVarInject();
        /*wait until turn off wdg,delay 3 clk for 32K * 1.5 */
        ++tms;
        wdtSta = ((REG_READ32(base + WDT_CTRL_OFF) >> offset) & WDG_IP_FUNCTION_ENABLE);
        WdgHookEnd_TimeoutVarInject();
    }

    WdgHookEnd_Wdg_Ip_TimeoutCheck();
    if (tms < count)
    {
        ret = E_OK;
    } /*else not use*/

    return ret;
}


/** *****************************************************************************************************
 * \brief This service set base wdg mode off for the WDG driver.
 *
 * \verbatim
 * Syntax             : static Std_ReturnType Wdg_Ip_SetModeOff(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base  - Wdg Instance id base Addr
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : E_OK\E_NOT_OK
 *
 * Description        : This service set base wdg mode off for the WDG driver.
 * \endverbatim
 * Traceability       : SWSR_WDG_007 SWSR_WDG_011 SWSR_WDG_012 SWSR_WDG_013
 *                      SWSR_WDG_014 SW_SM005
 *******************************************************************************************************/
static Std_ReturnType Wdg_Ip_SetModeOff(uint32 base)
{
    Std_ReturnType  retVal;
    uint32 regVal;

    /*#10 disable wdt*/
    regVal = REG_READ32(base + WDT_CTRL_OFF);
    REG_WRITE32((regVal & ~BM_WDT_CTRL_WDT_EN), base + WDT_CTRL_OFF);
    retVal = Wdg_Ip_WaitCtrlBaseState(base, WDT_CTRL_WDT_EN_STA_OFF, WDG_IP_FUNCTION_DISABLE);

    if (E_OK == retVal)
    {
        regVal = REG_READ32(base + WDT_INT_OFF);
        REG_WRITE32((regVal & ~BM_WDT_INT_EN), base + WDT_INT_OFF);
    } /*else not use*/

    return retVal;
}

/** *****************************************************************************************************
 * \brief This service set base wdg enable for the WDG driver.
 *
 * \verbatim
 * Syntax             : static Std_ReturnType Wdg_Ip_SetWdtEnable(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base  - Wdg Instance id base Addr
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : E_OK\E_NOT_OK
 *
 * Description        : This service set base wdg enable for the WDG driver.
 * \endverbatim
 * Traceability       : SWSR_WDG_007 SWSR_WDG_011 SWSR_WDG_012 SWSR_WDG_013
 *                      SWSR_WDG_014 SW_SM005
 *******************************************************************************************************/
static Std_ReturnType Wdg_Ip_SetWdtEnable(uint32 base)
{
    Std_ReturnType  retVal;
    uint32 regVal;

    /*#10 enable wdt*/
    regVal = REG_READ32(base + WDT_CTRL_OFF) | BM_WDT_CTRL_WDT_EN;
    REG_WRITE32(regVal, base + WDT_CTRL_OFF);

    /*#20 wait wdt enable complete*/
    retVal = Wdg_Ip_WaitCtrlBaseState(base, WDT_CTRL_WDT_EN_STA_OFF, WDG_IP_FUNCTION_ENABLE);

    /*#30 enable soft reset*/
    if (E_OK == retVal)
    {
        regVal = REG_READ32(base + WDT_CTRL_OFF) | BM_WDT_CTRL_SOFT_RST;
        REG_WRITE32(regVal, base + WDT_CTRL_OFF);

        /*#40 wait wdt soft reset complete*/
        retVal = Wdg_Ip_WaitCtrlBaseState(base, WDT_CTRL_SOFT_RST_OFF, WDG_IP_FUNCTION_DISABLE);
    } /*else not use*/

    return retVal;
}
/** *****************************************************************************************************
 * \brief This service set base wdg work mode for the WDG driver.
 *
 * \verbatim
 * Syntax             : static void Wdg_Ip_SetTriggerConditionMode
 *                      (Wdg_TriggerConditionType triggerCondition,uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base  - Wdg Instance id base Addr
 *
 * Parameters (in)    : triggerCondition  - Wdg work mode window or normal mode
 *
 * Parameters (in)    : refreshTime  - Wdg when only work window refresh time,
 *                                     refreshTime~initTimeout is feed dog time
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This service set base wdg work mode for the WDG driver.
 * \endverbatim
 * Traceability       : SWSR_WDG_019
 *******************************************************************************************************/
static void Wdg_Ip_SetTriggerConditionMode(Wdg_TriggerConditionType triggerCondition,
        uint32 refreshTime, uint32 base)
{
    /*#10 wdt trigger mode setting*/
    if (NO_CONDITION_MODE == triggerCondition)
    {
        /*#20 wdt normal trigger mode setting*/
        REG_WRITE32(BM_WDT_WRC_CTL_MODE0_EN, base + WDT_WRC_CTL_OFF);
    }
    else
    {
        /*#30 wdt window trigger mode setting*/
        REG_WRITE32((refreshTime + WDT_IP_CNT_COUNT), base + WDT_WRC_VAL_OFF);
        REG_WRITE32((BM_WDT_WRC_CTL_MODE1_EN) | (BM_WDT_WRC_CTL_MODE0_EN), base + WDT_WRC_CTL_OFF);
    }
}

/** *****************************************************************************************************
 * \brief This service set base wdg wtc value function Enable for the WDG driver.
 *
 * \verbatim
 * Syntax             : static Std_ReturnType Wdg_Ip_WdtWtc
 *                      (uint32 base,uint32 clockFrequency,uint32 initTimeout,uint8 instanceId)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base  - Wdg Instance id base Addr
 *
 * Parameters (in)    : clockFrequency  - Wdg Instance id clk frequence
 *
 * Parameters (in)    : initTimeout  - User time out value(ms) setting
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : E_OK\E_NOT_OK
 *
 * Description        : This service set base wdg wtc value function Enable for the WDG driver.
 * \endverbatim
 * Traceability       : SWSR_WDG_008 SWSR_WDG_021 SWSR_WDG_029 SWSR_WDG_030 SWSR_WDG_031
 *                      SWSR_WDG_032 SWSR_WDG_033 SWSR_WDG_034
 *******************************************************************************************************/
static void Wdg_Ip_WdtWtc(uint32 base, uint32 clockFrequency, uint32 initTimeout,
                                    uint8 instanceId)
{
    uint32 regVal;
    uint32 timeRatio;

    /*#10 wtc value calculate*/
    regVal = REG_READ32(base + WDT_CTRL_OFF);

    regVal &= ~FM_WDT_CTRL_PRE_DIV_NUM;
    /*#20 clk div setting */
    if (WDT9_INDEX == instanceId)
    {
        timeRatio = clockFrequency / WDG_IP_CLK_FREQUENCE_LP;
        Wdg_Ip_SetTimeRatio(timeRatio, instanceId);
        regVal |= (uint32)(FV_WDT_CTRL_PRE_DIV_NUM(WDG_IP_CLK_DIV_NUM_LP));
    }
    else
    {
        timeRatio = clockFrequency / WDG_IP_CLK_FREQUENCE_SF;
        WdgHookBegin_InvalidInstanceSetRatioInject();
        Wdg_Ip_SetTimeRatio(timeRatio, instanceId);
        WdgHookEnd_InvalidInstanceSetRatioInject();
        regVal |= (uint32)(FV_WDT_CTRL_PRE_DIV_NUM(WDG_IP_CLK_DIV_NUM_SF));
    }
#if (WDG_DEBUG_SUPPORT == STD_ON)
    regVal |= BM_WDT_CTRL_DBG_HALT_EN;
#endif /*WDG_DEBUG_SUPPORT*/
    /*#30 wtc src enable*/
    regVal |= BM_WDT_CTRL_WTC_SRC;
    REG_WRITE32(regVal, base + WDT_CTRL_OFF);
    /*#40 wtc value setting*/
    regVal = ((uint32)initTimeout + WDT_IP_CNT_COUNT) * Wdg_Ip_GetTimeRatio(instanceId);

    REG_WRITE32(regVal, base + WDT_WTC_OFF);
    /* Using main_clk: source clock is ss 24M*/
    regVal = REG_READ32(base + WDT_CTRL_OFF) & ~FM_WDT_CTRL_CLK_SRC;
    REG_WRITE32(regVal, base + WDT_CTRL_OFF);

    return;
}

/** *****************************************************************************************************
 * \brief This service set base wdg timeout extern singnal function Enable for the WDG driver.
 *
 * \verbatim
 * Syntax             : static void Wdg_Ip_WdtExternSignalEnable(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base  - Wdg Instance id base Addr
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This service set base wdg timeout extern singnal function Enable for the WDG driver.
 * \endverbatim
 * Traceability       : SWSR_WDG_080
 *******************************************************************************************************/
static void Wdg_Ip_WdtExternSignalEnable(uint32 base)
{
    uint32 regVal;

    /*#10 external signal output enable setting*/
    regVal = REG_READ32(base + WDT_EXT_RST_CTL_OFF) & ~BM_WDT_EXT_RST_CTL_EXT_RST_MODE;
    REG_WRITE32(regVal, base + WDT_EXT_RST_CTL_OFF);
    regVal = REG_READ32(base + WDT_EXT_RST_CTL_OFF) | BM_WDT_EXT_RST_CTL_EXT_RST_EN;
    REG_WRITE32(regVal, base + WDT_EXT_RST_CTL_OFF);
}

/** *****************************************************************************************************
 * \brief This service set base wdg init for the WDG driver.
 *
 * \verbatim
 * Syntax             : static Std_ReturnType Wdg_Ip_WdtCtrolInit(uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : base  - Wdg Instance id base Addr
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : E_OK\E_NOT_OK
 *
 * Description        : This service set base wdg init for the WDG driver.
 * \endverbatim
 * Traceability       : SWSR_WDG_079 SW_SM005
 *******************************************************************************************************/
static Std_ReturnType Wdg_Ip_WdtCtrolInit(uint32 base)
{
    Std_ReturnType  retVal;
    uint32 regVal;

    /*#10 clear wdt enable bit and select wdt enable source*/
    regVal = REG_READ32(base + WDT_CTRL_OFF) & ~BM_WDT_CTRL_WDT_EN;
    REG_WRITE32(regVal, base + WDT_CTRL_OFF);
    regVal = REG_READ32(base + WDT_CTRL_OFF) | BM_WDT_CTRL_WDT_EN_SRC;
    REG_WRITE32(regVal, base + WDT_CTRL_OFF);

    /*#20 wait wdt enable bit setting complete*/
    retVal = Wdg_Ip_WaitCtrlBaseState(base, WDT_CTRL_WDT_EN_STA_OFF, WDG_IP_FUNCTION_DISABLE);

    /*#30 wdt reset bit setting*/
    if (E_OK == retVal)
    {
        regVal = REG_READ32(base + WDT_RST_CTL_OFF) | BM_WDT_RST_CTL_WDT_RST_EN;
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
    } /*else not use*/

    return retVal;
}

/** *****************************************************************************************************
 * \brief This service set wdg timeort behavior for the WDG driver.
 *
 * \verbatim
 * Syntax             : static void Wdg_Ip_SetTimeOutBehavior
 *                             (const Wdg_ModeConfigType *pModeSetting, Wdg_TimeoutBehaviorType timeoutBehavior,uint32 base)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : timeoutBehavior - Wdg timeout Behavior.
 *
 * Parameters (in)    : base  - Wdg Instance id base Addr
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This service set wdg timeort behavior for the WDG driver.
 * \endverbatim
 * Traceability       : SWSR_WDG_075
 *******************************************************************************************************/
static void Wdg_Ip_SetTimeOutBehavior(const Wdg_ModeConfigType *pModeSetting,
                                      Wdg_TimeoutBehaviorType timeoutBehavior,
                                      uint32 base)
{
    uint32 regVal;
    /*#10 timeoutBehavior behavior setting*/
    if (WDG_INTERRUPT == timeoutBehavior)
    {
        /* enable timeout interrupt and disable wdt reset function*/
        regVal = REG_READ32(base + WDT_INT_OFF) | BM_WDT_INT_EN;
        REG_WRITE32(regVal, base + WDT_INT_OFF);
        regVal = REG_READ32(base + WDT_RST_CTL_OFF) & ~BM_WDT_RST_CTL_INT_RST_EN;
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
        /*auto restart enable*/
        regVal = REG_READ32(base + WDT_CTRL_OFF) | BM_WDT_CTRL_AUTO_RESTART;
        REG_WRITE32(regVal, base + WDT_CTRL_OFF);
    }

    if (WDG_RESET == timeoutBehavior)
    {
        /*auto restart disable*/
        regVal = REG_READ32(base + WDT_CTRL_OFF) & ~BM_WDT_CTRL_AUTO_RESTART;
        REG_WRITE32(regVal, base + WDT_CTRL_OFF);
        /* default Level mode */
        /* disable timeout interrupt and enable wdt reset function*/
        regVal = REG_READ32(base + WDT_INT_OFF) & ~BM_WDT_INT_EN;
        REG_WRITE32(regVal, base + WDT_INT_OFF);
        /*Set delay time between overflow and reset. Maxium 2.7ms for 24MHz reference clk.*/
        regVal = REG_READ32(base + WDT_RST_CTL_OFF);
        regVal &= ~FM_WDT_RST_CTL_RST_CNT;
        regVal |= FV_WDT_RST_CTL_RST_CNT(pModeSetting->overflowToResetCntVal);
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
        /*Set offset of delay time between overflow and reset.*/
        regVal = REG_READ32(base + WDT_RST_CTL_OFF) |
                FV_WDT_RST_CTL_RST_CNT_SHIFTER(pModeSetting->overflowToResetCntValOffset);
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
        regVal = REG_READ32(base + WDT_RST_CTL_OFF) | FM_WDT_RST_CTL_RST_WIN;
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
        regVal = REG_READ32(base + WDT_RST_CTL_OFF) | BM_WDT_RST_CTL_INT_RST_EN;
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
    }

    if (WDG_BOTH == timeoutBehavior)
    {
        /*auto restart disable*/
        regVal = REG_READ32(base + WDT_CTRL_OFF) & ~BM_WDT_CTRL_AUTO_RESTART;
        REG_WRITE32(regVal, base + WDT_CTRL_OFF);
        /* enable timeout interrupt and enable wdt reset function*/
        regVal = REG_READ32(base + WDT_INT_OFF) | BM_WDT_INT_EN;
        REG_WRITE32(regVal, base + WDT_INT_OFF);
        /*Set delay time between overflow and reset. Maxium 2.7ms for 24MHz reference clk.*/
        regVal = REG_READ32(base + WDT_RST_CTL_OFF);
        regVal &= ~FM_WDT_RST_CTL_RST_CNT;
        regVal |= FV_WDT_RST_CTL_RST_CNT(pModeSetting->overflowToResetCntVal);
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
        /*Set offset of delay time between overflow and reset.*/
        regVal = REG_READ32(base + WDT_RST_CTL_OFF) |
                FV_WDT_RST_CTL_RST_CNT_SHIFTER(pModeSetting->overflowToResetCntValOffset);
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
        regVal = REG_READ32(base + WDT_RST_CTL_OFF) | FM_WDT_RST_CTL_RST_WIN;
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
        regVal = REG_READ32(base + WDT_RST_CTL_OFF) | BM_WDT_RST_CTL_INT_RST_EN;
        REG_WRITE32(regVal, base + WDT_RST_CTL_OFF);
    }
}

#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
/*need comments*/
static void Wdg_Ip_SetRefreshTimeoutCounter(uint16 timeout, uint16 gptPerid, uint8 instanceId)
{
    /*PRQA S 3352 56*/
    switch (instanceId)
    {
        /*#10 calculate Wdg1_TimeoutCounter*/
#if (WDG_INSTANCE1_SUPPORT == STD_ON)

    case WDT1_INDEX:
        Wdg1_TimeoutCounter = (uint32)((uint32)timeout / (uint32)gptPerid);
        break;
#endif /*WDG_INSTANCE1_SUPPORT*/
        /*#20 calculate Wdg2_TimeoutCounter*/
#if (WDG_INSTANCE2_SUPPORT == STD_ON)

    case WDT2_INDEX:
        Wdg2_TimeoutCounter = (uint32)((uint32)timeout / (uint32)gptPerid);
        break;
#endif /*WDG_INSTANCE2_SUPPORT*/
        /*#30 calculate Wdg3_TimeoutCounter*/
#if (WDG_INSTANCE3_SUPPORT == STD_ON)

    case WDT3_INDEX:
        Wdg3_TimeoutCounter = (uint32)((uint32)timeout / (uint32)gptPerid);
        break;
#endif /*WDG_INSTANCE3_SUPPORT*/
        /*#40 calculate Wdg4_TimeoutCounter*/
#if (WDG_INSTANCE4_SUPPORT == STD_ON)

    case WDT4_INDEX:
        Wdg4_TimeoutCounter = (uint32)((uint32)timeout / (uint32)gptPerid);
        break;
#endif /*WDG_INSTANCE4_SUPPORT*/
        /*#50 calculate Wdg5_TimeoutCounter*/
#if (WDG_INSTANCE5_SUPPORT == STD_ON)

    case WDT5_INDEX:
        Wdg5_TimeoutCounter = (uint32)((uint32)timeout / (uint32)gptPerid);
        break;
#endif /*WDG_INSTANCE5_SUPPORT*/
        /*#60 calculate Wdg6_TimeoutCounter*/
#if (WDG_INSTANCE6_SUPPORT == STD_ON)

    case WDT6_INDEX:
        Wdg6_TimeoutCounter = (uint32)((uint32)timeout / (uint32)gptPerid);
        break;
#endif /*WDG_INSTANCE6_SUPPORT*/
        /*#70 calculate Wdg8_TimeoutCounter*/
#if (WDG_INSTANCE8_SUPPORT == STD_ON)

    case WDT8_INDEX:
        Wdg8_TimeoutCounter = (uint32)((uint32)timeout / (uint32)gptPerid);
        break;
#endif /*WDG_INSTANCE8_SUPPORT*/
        /*#80 calculate Wdg9_TimeoutCounter*/
#if (WDG_INSTANCE9_SUPPORT == STD_ON)

    case WDT9_INDEX:
        Wdg9_TimeoutCounter = (uint32)((uint32)timeout / (uint32)gptPerid);
        break;
#endif /*WDG_INSTANCE9_SUPPORT*/

    default:
        /*do nothing*/
        break;
    }

}
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */

/** *****************************************************************************************************
 * \brief This service initializes the WDG driver.
 *
 * \verbatim
 * Syntax             : void Wdg_Ip_Init
 *                      (const Wdg_ModeConfigType *pModeSetting, uint16 initTimeout, uint8 instanceId)
 *
 * Service ID[hex]    : 0x00
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : pModeSetting - Pointer to WDG driver mode configuration set.
 *
 * Parameters (in)    : initTimeout - init wdg time out.
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : E_OK/E_NOT_OK
 *
 * Description        : Driver Module Initialization function.The Initialization function shall
 *                      initialize all WDG relevant registers with the values of the structure
 *                      referenced by the parameter configPtr
 * \endverbatim
 * Traceability       : SWSR_WDG_007 SWSR_WDG_009 SWSR_WDG_011 SWSR_WDG_012 SWSR_WDG_013 SW_SM005
 *                      SWSR_WDG_014 SWSR_WDG_015 SWSR_WDG_016 SWSR_WDG_017 SWSR_WDG_018
 *                      SWSR_WDG_020 SWSR_WDG_037 SWSR_WDG_072 SWSR_WDG_073 SWSR_WDG_078
 *******************************************************************************************************/
Std_ReturnType Wdg_Ip_Init(const Wdg_ModeConfigType *pModeSetting, uint16 initTimeout,
                           uint8 instanceId)
{
    Std_ReturnType retVal;
#if (STD_ON == WDG_CTRL_REG_LOCK_ALLOWED)
    uint32 regVal;
#endif

    WdgHookBegin_Wdg_Init();

    uint32 base = Wdg_Ip_GetBaseAddr(instanceId);

    /*#10 wdg register init*/
    retVal = Wdg_Ip_WdtCtrolInit(base);

    if (E_OK == retVal)
    {
        /*#20 wdg TimeOut Behavior setting*/
        Wdg_Ip_SetTimeOutBehavior(pModeSetting, pModeSetting->timeoutBehavior, base);
    }/*else not to use*/

    /* Level mode */
    if (TRUE == pModeSetting->externalSignalEnable)
    {
        /*#30 wdg TimeOut external signal output setting*/
        Wdg_Ip_WdtExternSignalEnable(base);
    }/*else not to use*/

#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)

    if (E_OK == retVal)
    {
        Wdg_Ip_SetRefreshTimeoutCounter(initTimeout, pModeSetting->setTriggerConditionWithGptPeriod,
                                        instanceId);
    }

#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */

    if (E_OK == retVal)
    {
        if (WDT_IP_ZERO != pModeSetting->clockFrequency)
        {
            /*#40 wdg TimeOut value setting*/
            Wdg_Ip_WdtWtc(base, pModeSetting->clockFrequency, (uint32)initTimeout, instanceId);

            /*PRQA S 2991,2995 2*/
            /*#50 wdg trigger mode setting*/
            Wdg_Ip_SetTriggerConditionMode(pModeSetting->triggerCondition, pModeSetting->refreshTime,
                                            base);
            /*#60 wdg start work*/
            retVal = Wdg_Ip_SetWdtEnable(base);
        }/*else not to use*/
    }/*else not to use*/

#if (STD_ON == WDG_CTRL_REG_LOCK_ALLOWED)
    regVal = REG_READ32(base + WDT_LOCK_OFF) | BM_WDT_LOCK_CTL_LOCK;
    REG_WRITE32(regVal, base + WDT_LOCK_OFF);
#endif

    WdgHookEnd_Wdg_Init();

    return retVal;
}

/** *****************************************************************************************************
 * \brief This function triggers the servicing of the watchdog.
 *
 * \verbatim
 * Syntax             : Std_ReturnType Wdg_Ip_SetMode(const Wdg_ModeConfigType *pModeSetting, uint8 instanceId)
 *
 * Service ID[hex]    : 0x01
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : pModeSetting - Pointer to WDG driver mode configuration set.
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       :  E_NOT_OK/E_OK
 *
 * Description        : Always returns E_OK, Wdg_SetMode is made available because
 *                      WDG Interface layer expects this function to be present.
 * \endverbatim
 * Traceability       : SWSR_WDG_005 SWSR_WDG_006 SWSR_WDG_007 SWSR_WDG_009 SWSR_WDG_010
 *                      SWSR_WDG_019 SWSR_WDG_020 SWSR_WDG_021 SWSR_WDG_022 SWSR_WDG_023
 *                      SWSR_WDG_024 SWSR_WDG_025 SWSR_WDG_026 SWSR_WDG_027 SWSR_WDG_028
 *                      SWSR_WDG_044 SWSR_WDG_073 SWSR_WDG_078 SW_SM005
 *******************************************************************************************************/
Std_ReturnType Wdg_Ip_SetMode(const Wdg_ModeConfigType *pModeSetting, uint8 instanceId)
{
    Std_ReturnType retVal;
    uint32 regVal;
    uint32 base = Wdg_Ip_GetBaseAddr(instanceId);

    /*#10 wdt enable source select*/
    regVal = REG_READ32(base + WDT_CTRL_OFF) | BM_WDT_CTRL_WDT_EN_SRC;
    REG_WRITE32(regVal, base + WDT_CTRL_OFF);
    /*#20 wdg TimeOut Behavior setting*/
    Wdg_Ip_SetTimeOutBehavior(pModeSetting, pModeSetting->timeoutBehavior, base);

    /* Level mode */
    if (TRUE == pModeSetting->externalSignalEnable)
    {
        /*#30 wdg TimeOut external signal output setting*/
        Wdg_Ip_WdtExternSignalEnable(base);
    }/*else not to use*/

#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
    Wdg_Ip_SetRefreshTimeoutCounter((uint16)(pModeSetting->timeoutPeriod),
                                    pModeSetting->setTriggerConditionWithGptPeriod, instanceId);
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */

    if (WDT_IP_ZERO != pModeSetting->clockFrequency)
    {
        /*#40 wdg TimeOut value setting*/
        Wdg_Ip_WdtWtc(base, pModeSetting->clockFrequency, (uint32)pModeSetting->timeoutPeriod,
                               instanceId);

        /*PRQA S 2991,2995 2*/
        /*#50 wdg trigger mode setting*/
        Wdg_Ip_SetTriggerConditionMode(pModeSetting->triggerCondition, pModeSetting->refreshTime,
                                        base);
        /*#60 wdg start work*/
        retVal = Wdg_Ip_SetWdtEnable(base);
    }
    else
    {
        /*#70 wdg start mode off work*/
        retVal = Wdg_Ip_SetModeOff(base);
    }

    return retVal;
}

/** *****************************************************************************************************
 * \brief Sets the timeout value for the trigger counter.
 *
 * \verbatim
 * Syntax             : void Wdg_Ip_SetTriggerCondition(uint16 timeout, uint8 instanceId)
 *
 * Service ID[hex]    : 0x03
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : timeout - Timeout value (milliseconds) for setting the trigger counter
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : Always returns E_OK, Wdg_SetMode is made available because
 *                      WDG Interface layer expects this function to be present.
 * \endverbatim
 * Traceability       : SWSR_WDG_008 SWSR_WDG_009 SWSR_WDG_029 SWSR_WDG_030 SWSR_WDG_031
 *                      SWSR_WDG_032 SWSR_WDG_033 SWSR_WDG_034 SWSR_WDG_051 SWSR_WDG_073
 *                      SWSR_WDG_075
 *******************************************************************************************************/
#if (STD_OFF == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
void Wdg_Ip_SetTriggerCondition(uint16 timeout, uint8 instanceId)
{
    uint32 base = Wdg_Ip_GetBaseAddr(instanceId);
    uint8  i;
    uint32 regVal;

    /*#10 switch wtc_src to 0*/
    regVal = REG_READ32(base + WDT_CTRL_OFF) & ~BM_WDT_CTRL_WTC_SRC;
    REG_WRITE32(regVal, base + WDT_CTRL_OFF);

    /*#20 wait more than 4*wdt clock to set wtc_src bit*/
    for (i = 0; i < WDG_IP_WAIT_TIMEOUT_TIME; i++)
    {
        REG_READ32(base + WDT_CTRL_OFF);
    }

    /*#30 trigger wdt*/
    regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
    REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);

    /*#40 set timeout value*/
    /*For SWS_Wdg_00140, if users pass '0',wdg will almost reset immediately*/
    if (WDG_IP_MIN_TIME_VAL == timeout)
    {
        REG_WRITE32(0x1UL, base + WDT_WTC_OFF);
    }
    else
    {
        REG_WRITE32(((uint32)timeout + WDT_IP_CNT_COUNT) * Wdg_Ip_GetTimeRatio(instanceId),
                    base + WDT_WTC_OFF);
    }

    /*#50 switch wtc_src to 1*/
    regVal = REG_READ32(base + WDT_CTRL_OFF) | BM_WDT_CTRL_WTC_SRC;
    REG_WRITE32(regVal, base + WDT_CTRL_OFF);

    /*#60 wait more than 4*wdt clock to set wtc_src bit*/
    for (i = 0; i < WDG_IP_WAIT_TIMEOUT_TIME; i++)
    {
        REG_READ32(base + WDT_CTRL_OFF);
    }

    /*70# retrigger wdt*/
    regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
    REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
}
#else
void Wdg_Ip_SetTriggerCondition(const Wdg_ModeConfigType *pModeSetting, uint16 timeout,
                                uint8 instanceId)
{
    uint8  i;
    uint32 regVal;

    uint32 base = Wdg_Ip_GetBaseAddr(instanceId);

    /*#10 null point check*/
    if (NULL_PTR != pModeSetting)
    {

        if (WDG_IP_MIN_TIME_VAL != timeout)
        {

            /*#20 set Wdg TimeoutCounter value*/
            Wdg_Ip_SetRefreshTimeoutCounter(timeout, pModeSetting->setTriggerConditionWithGptPeriod,
                                            instanceId);

            /*#30 feed dog*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
        }
        else
        {
            /*#20 switch wtc_src to 0*/
            regVal = REG_READ32(base + WDT_CTRL_OFF) & ~BM_WDT_CTRL_WTC_SRC;
            REG_WRITE32(regVal, base + WDT_CTRL_OFF);

            /*#30 wait more than 4*wdt clock to set wtc_src bit*/
            for (i = 0; i < WDG_IP_WAIT_TIMEOUT_TIME; i++)
            {
                REG_READ32(base + WDT_CTRL_OFF);
            }

            /*#40 trigger wdt*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);

            /*#50 set timeout value*/
            /*For SWS_Wdg_00140, if users pass '0',wdg will almost reset immediately*/
            REG_WRITE32(0x1UL, base + WDT_WTC_OFF);

            /*60# switch wtc_src to 1*/
            regVal = REG_READ32(base + WDT_CTRL_OFF) | BM_WDT_CTRL_WTC_SRC;
            REG_WRITE32(regVal, base + WDT_CTRL_OFF);

            /*#70 wait more than 4*wdt clock to set wtc_src bit*/
            for (i = 0; i < WDG_IP_WAIT_TIMEOUT_TIME; i++)
            {
                REG_READ32(base + WDT_CTRL_OFF);
            }

            /*80# retrigger wdt*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
        }
    }

}
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */
#define WDG_STOP_SEC_CODE
#include "Wdg_MemMap.h"

/** *****************************************************************************************************
 * \brief This function Wdg Ip clear interrupt state.
 *
 * \verbatim
 * Syntax             : void Wdg_Ip_ClearInterruptFlag(uint8 instanceId)
 *
 * Service ID[hex]    : none
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This function Wdg Ip clear interrupt state.
 * \endverbatim
 * Traceability       : SWSR_WDG_074
 *******************************************************************************************************/
#define WDG_START_SEC_CODE_FAST
#include "Wdg_MemMap.h"
void Wdg_Ip_ClearInterruptFlag(uint8 instanceId)
{
    uint32 base = Wdg_Ip_GetBaseAddr(instanceId);
    uint32 regVal;

    /*#10 clear interrupt bit*/
    regVal = REG_READ32(base + WDT_INT_OFF) | BM_WDT_INT_STA_CLR;
    REG_WRITE32(regVal, base + WDT_INT_OFF);
}

/** *****************************************************************************************************
 * \brief This function checks if wdt HW interrupt as expected or not
 *
 * \verbatim
 * Syntax             : Std_ReturnType Wdg_Ip_ExpectedInterruptCheck(uint8 instanceId)
 *
 * Service ID[hex]    : none
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : E_NOT_OK/E_OK
 *
 * Description        : This function checks if wdt HW interrupt as expected or not
 * \endverbatim
 * Traceability       : SW_SM004
 *******************************************************************************************************/
Std_ReturnType Wdg_Ip_ExpectedInterruptCheck(uint8 instanceId)
{
    Std_ReturnType ret;
    uint32 enable;
    uint32 state;
    uint32 base = Wdg_Ip_GetBaseAddr(instanceId);

    /*#10 obtain wdt interrupt enable bit and interrut state*/
    enable = (REG_READ32(base + WDT_INT_OFF) & BM_WDT_INT_EN) >> WDT_INT_FUNC_EN_OFF;
    state = (REG_READ32(base + WDT_INT_OFF) & BM_WDT_INT_STA) >> WDT_INT_STA_OFF;

    WdgHookBegin_InterruptCheckInject();
    /*#20 judge whether it is expect interrupt*/
    if ((enable & state) > WDT_IP_ZERO)
    {
        ret = E_OK;
    }
    else
    {
        ret = E_NOT_OK;
    }
    WdgHookEnd_InterruptCheckInject();
    return ret;
}
#define WDG_STOP_SEC_CODE_FAST
#include "Wdg_MemMap.h"

/** *****************************************************************************************************
 * \brief This function triggers the servicing of the watchdog and feed dog.
 *
 * \verbatim
 * Syntax             : void Wdg_Ip_TriggerRoutine(uint8 instanceId)
 *
 * Service ID[hex]    : 0x05
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : instanceId  - Wdg Instance id and it is depending on hardware id
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This function is the watchdog trigger
 * \endverbatim
 * Traceability       : SWSR_WDG_008 SWSR_WDG_009 SWSR_WDG_031 SWSR_WDG_051 SW_SM002 SW_SM001
 *                      SWSR_WDG_058 SWSR_WDG_073 SWSR_WDG_075
 *******************************************************************************************************/
#define WDG_START_SEC_CODE
#include "Wdg_MemMap.h"
void Wdg_Ip_TriggerRoutine(uint8 instanceId)
{
    uint32 base = Wdg_Ip_GetBaseAddr(instanceId);
    uint32 regVal;

    /*#10 trigger wdt*/
    regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
    REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
}

#if (STD_ON == WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED)
/** *****************************************************************************************************
 * \brief This service handles timeout counter when using SetTriggerCondition with gpt
 *
 * \verbatim
 * Syntax             : uint32 Wdg_Ip_SetTriggerConditionHandler(uint8 instanceId)
 *
 * Service ID[hex]    : None
 *
 * Sync/Async         : Synchronous
 *
 * Reentrancy         : Non reentrant
 *
 * Parameters (in)    : None
 *
 * Parameters (inout) : None
 *
 * Parameters (out)   : None
 *
 * Return value       : None
 *
 * Description        : This service handles timeout counter when using SetTriggerCondition with gpt.
 *
 * \endverbatim
 * Traceability       : SWSR_WDG_003 SWSR_WDG_008 SWSR_WDG_009 SWSR_WDG_029 SWSR_WDG_030
 *                      SWSR_WDG_032 SWSR_WDG_033 SWSR_WDG_034 SWSR_WDG_051 SWSR_WDG_073
 *                      SWSR_WDG_075 SWSR_WDG_078 SW_SM002 SW_SM001 SW_SM006 SWSR_WDG_031
 *                      SWSR_WDG_083
 *******************************************************************************************************/
uint32 Wdg_Ip_SetTriggerConditionHandler(uint8 instanceId)
{
    uint32 timeoutCounter = 0;
    uint32 regVal;

    uint32 base = Wdg_Ip_GetBaseAddr(instanceId);

    /*#10 null point check*/
    /*PRQA S 3352 115*/
    switch (instanceId)
    {

#if (WDG_INSTANCE1_SUPPORT == STD_ON)

    case WDT1_INDEX:
        if (WDT_IP_ZERO != Wdg1_TimeoutCounter)
        {
            /*#20 Wdg1_TimeoutCounter minus*/
            Wdg1_TimeoutCounter --;
            /*#30 feed wdg*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
            /*#40 assign Wdg1_TimeoutCounter to timeoutCounter*/
            timeoutCounter = Wdg1_TimeoutCounter;
        }

        break;
#endif /*WDG_INSTANCE1_SUPPORT*/
#if (WDG_INSTANCE2_SUPPORT == STD_ON)

    case WDT2_INDEX:
        if (WDT_IP_ZERO != Wdg2_TimeoutCounter)
        {
            /*#20 Wdg2_TimeoutCounter minus*/
            Wdg2_TimeoutCounter --;
            /*#30 feed wdg*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
            /*#40 assign Wdg2_TimeoutCounter to timeoutCounter*/
            timeoutCounter = Wdg2_TimeoutCounter;
        }

        break;
#endif /*WDG_INSTANCE2_SUPPORT*/
#if (WDG_INSTANCE3_SUPPORT == STD_ON)

    case WDT3_INDEX:
        if (WDT_IP_ZERO != Wdg3_TimeoutCounter)
        {
            /*#20 Wdg3_TimeoutCounter minus*/
            Wdg3_TimeoutCounter --;
            /*#30 feed wdg*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
            /*#40 assign Wdg3_TimeoutCounter to timeoutCounter*/
            timeoutCounter = Wdg3_TimeoutCounter;
        }

        break;
#endif /*WDG_INSTANCE3_SUPPORT*/
#if (WDG_INSTANCE4_SUPPORT == STD_ON)

    case WDT4_INDEX:
        if (WDT_IP_ZERO != Wdg4_TimeoutCounter)
        {
            /*#20 Wdg4_TimeoutCounter minus*/
            Wdg4_TimeoutCounter --;
            /*#30 feed wdg*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
            /*#40 assign Wdg4_TimeoutCounter to timeoutCounter*/
            timeoutCounter = Wdg4_TimeoutCounter;
        }

        break;
#endif /*WDG_INSTANCE4_SUPPORT*/
#if (WDG_INSTANCE5_SUPPORT == STD_ON)

    case WDT5_INDEX:
        if (WDT_IP_ZERO != Wdg5_TimeoutCounter)
        {
            /*#20 Wdg5_TimeoutCounter minus*/
            Wdg5_TimeoutCounter --;
            /*#30 feed wdg*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
            /*#40 assign Wdg5_TimeoutCounter to timeoutCounter*/
            timeoutCounter = Wdg5_TimeoutCounter;
        }

        break;
#endif /*WDG_INSTANCE5_SUPPORT*/
#if (WDG_INSTANCE6_SUPPORT == STD_ON)

    case WDT6_INDEX:
        if (WDT_IP_ZERO != Wdg6_TimeoutCounter)
        {
            /*#20 Wdg6_TimeoutCounter minus*/
            Wdg6_TimeoutCounter --;
            /*#30 feed wdg*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
            /*#40 assign Wdg6_TimeoutCounter to timeoutCounter*/
            timeoutCounter = Wdg6_TimeoutCounter;
        }

        break;
#endif /*WDG_INSTANCE6_SUPPORT*/
#if (WDG_INSTANCE8_SUPPORT == STD_ON)

    case WDT8_INDEX:
        if (WDT_IP_ZERO != Wdg8_TimeoutCounter)
        {
            /*#20 Wdg8_TimeoutCounter minus*/
            Wdg8_TimeoutCounter --;
            /*#30 feed wdg*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
            /*#40 assign Wdg8_TimeoutCounter to timeoutCounter*/
            timeoutCounter = Wdg8_TimeoutCounter;
        }

        break;
#endif /*WDG_INSTANCE8_SUPPORT*/
#if (WDG_INSTANCE9_SUPPORT == STD_ON)

    case WDT9_INDEX:
        if (WDT_IP_ZERO != Wdg9_TimeoutCounter)
        {
            /*#20 Wdg9_TimeoutCounter minus*/
            Wdg9_TimeoutCounter --;
            /*#30 feed wdg*/
            regVal = REG_READ32(base + WDT_WRC_CTL_OFF) | BM_WDT_WRC_CTL_REFR_TRIG;
            REG_WRITE32(regVal, base + WDT_WRC_CTL_OFF);
            /*#40 assign Wdg9_TimeoutCounter to timeoutCounter*/
            timeoutCounter = Wdg9_TimeoutCounter;
        }

        break;
#endif /*WDG_INSTANCE9_SUPPORT*/

    default:
        timeoutCounter = 0;
        break;
    }

    return timeoutCounter;
}
#endif /* WDG_SETTRIGGERCONDITION_WITH_GPT_ALLOWED */

#define WDG_STOP_SEC_CODE
#include "Wdg_MemMap.h"
#endif /* WDG_INSTANCE1_SUPPORT||WDG_INSTANCE2_SUPPORT||WDG_INSTANCE3_SUPPORT||WDG_INSTANCE4_SUPPORT||WDG_INSTANCE5_SUPPORT||WDG_INSTANCE6_SUPPORT||WDG_INSTANCE8_SUPPORT||WDG_INSTANCE9_SUPPORT */
#ifdef __cplusplus
}
#endif
/* End of file */
